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Rev. 1.0, Nov. 2010 K8A56(57)ET(B)(Z)C
256Mb C-die NOR FLASH
16M x16, Synch Burst Multi Bank SLC NOR Flash
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. 2009 Samsung Electronics Co., Ltd. All rights reserved.
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
History Draft Date Jul. 2010 14, Oct. 2010 2, Nov. 2010 18, Nov. 2010 Remark Target Preliminary Preliminary Final -
Rev. 1.0
Revision History
Revision No. 0.0 0.5 0.6 1.0 - Initial Draft. - Preliminary datasheet. - Added NOTE "Not 100% tested." for parameter "32-word Buffer Programming Time" in 18.4 Erase/Program Performance table. - Specification is finalized. Editor
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K8A56(57)15ET(B)(Z)C
256Mb C-die NOR FLASH 1
datasheet NOR FLASH MEMORY
Rev. 1.0
1.0 FEATURES................................................................................................................................................................. 5 2.0 GENERAL DESCRIPTION ......................................................................................................................................... 5 3.0 PIN DESCRIPTION .................................................................................................................................................... 5 4.0 BALL FBGA TOP VIEW (BALL DOWN) ..................................................................................................................... 6 5.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 7 6.0 ORDERING INFORMATION ...................................................................................................................................... 8 7.0 PRODUCT INTRODUCTION...................................................................................................................................... 11 8.0 COMMAND DEFINITIONS ......................................................................................................................................... 12 9.0 DEVICE OPERATION ................................................................................................................................................ 14 9.1 Read Mode .............................................................................................................................................................. 14 9.1.1 Asynchronous Read Mode................................................................................................................................ 14 9.1.1.1 Asynchronous Page Read Mode ................................................................................................................ 14 9.1.2 Synchronous (Burst) Read Mode...................................................................................................................... 14 9.1.2.1 Continuous Linear Burst Read.................................................................................................................... 14 9.2 Programmable Wait State ....................................................................................................................................... 15 9.3 Handshaking............................................................................................................................................................ 15 9.4 Set Burst Mode Configuration Register ................................................................................................................... 15 9.4.1 Programmable Wait State Configuration........................................................................................................... 15 9.4.2 Burst Read Mode Setting .................................................................................................................................. 15 9.4.3 RDY Configuration ............................................................................................................................................ 15 9.5 Autoselect Mode...................................................................................................................................................... 17 9.6 Standby Mode ......................................................................................................................................................... 17 9.7 Automatic Sleep Mode ............................................................................................................................................ 17 9.8 Output Disable Mode ............................................................................................................................................... 17 9.9 Block Protection & Unprotection.............................................................................................................................. 17 9.10 Hardware Reset..................................................................................................................................................... 17 9.11 Software Reset ...................................................................................................................................................... 18 9.12 Program ................................................................................................................................................................. 18 9.13 Accelerated Program ............................................................................................................................................. 18 9.14 Write Buffer Programming ..................................................................................................................................... 18 9.15 Accelerated Write Buffer Programming ................................................................................................................. 19 9.16 Chip Erase ............................................................................................................................................................. 19 9.17 Block Erase ........................................................................................................................................................... 19 9.18 Unlock Bypass....................................................................................................................................................... 19 9.19 Erase Suspend / Resume...................................................................................................................................... 20 9.20 Program Suspend / Resume ................................................................................................................................. 20 9.21 Read While Write Operation .................................................................................................................................. 20 9.22 OTP Block Region ................................................................................................................................................. 20 9.23 Low VCC Write Inhibit ........................................................................................................................................... 20 9.24 Write Pulse "Glitch" Protection .............................................................................................................................. 21 9.25 Logical Inhibit......................................................................................................................................................... 21 10.0 FLASH MEMORY STATUS FLAGS ......................................................................................................................... 22 11.0 DEEP POWER DOWN ............................................................................................................................................. 24 12.0 COMMON FLASH MEMORY INTERFACE .............................................................................................................. 25 13.0 ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 27 14.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND ) ..................................................... 27 15.0 DC CHARACTERISTICS................................................................................................................................... 28 16.0 CAPACITANCE (TA = 25 C, VCC = 1.8V, f = 1.0MHz)...................................................................................... 29 17.0 AC TEST CONDITION ...................................................................................................................................... 29 18.0 AC CHARACTERISTICS .......................................................................................................................................... 30 18.1 Synchronous/Burst Read.................................................................................................................................30 18.2 Asynchronous Read ........................................................................................................................................33 18.3 Erase/Program Operation................................................................................................................................37 18.4 Erase/Program Performance ...........................................................................................................................38
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
19.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE ................................................................... 44
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
2.0 GENERAL DESCRIPTION
Rev. 1.0
256M Bit (16M x16) Synch Burst , Multi Bank SLC NOR Flash Memory
1.0 FEATURES
* Single Voltage, 1.7V to 1.95V for Read and Write operations * Organization - 16,777,216 x 16 bit ( Word Mode Only) * Read While Program/Erase Operation * Multiple Bank Architecture - 16 Banks (16Mb Partition) * OTP Block : Extra 512-Word block * Read Access Time (@ CL=30pF) - Asynchronous Random Access Time : 100ns - Synchronous Random Access Time :95ns - Burst Access Time : 11ns(66Mhz) / 9ns(83Mhz) / 7ns (108MHz) / 6ns (133MHz) * Page Mode Operation 16Words Page access allows fast asynchronous read Page Read Access Time : 18ns(66/83Mhz) / 15ns(108/133Mhz) * Burst Length : - Continuous Linear Burst - Linear Burst : 8-word & 16-word with Wrap * Block Architecture - Uniform block part (K8A(56/57)15EZC) : Two hundred fifty-six 64Kword blocks - Boot block part (K8A(56/57)15ET(B)C) : Four 16Kword blocks and two hundred fifty-five 64Kword blocks (Bank 0 contains four 16 Kword blocks and fifteen 64Kword blocks, Bank 1 ~ Bank 15 contain two hundred forty 64Kword blocks) * Reduce program time using the VPP * Support 32-word Buffer Program * Power Consumption (Typical value, CL=30pF) - Synchronous Read Current : 35mA - Program/Erase Current : 25mA - Read While Program/Erase Current : 45mA - Standby Mode/Auto Sleep Mode : 30uA * Block Protection/Unprotection - Using the software command sequence - Last two boot blocks are protected by WP=VIL (Boot block part : K8A(56/57)15ET(B)C) - Last one block (BA255) is protected by WP=VIL (Uniform block part : K8A(56/57)15EZC) - All blocks are protected by VPP=VIL * Handshaking Feature - Provides host system with minimum latency by monitoring RDY * Erase Suspend/Resume * Program Suspend/Resume * Unlock Bypass Program/Erase * Hardware Reset (RESET) * Deep Power Down Mode * Data Polling and Toggle Bits - Provides a software method of detecting the status of program or erase completion * Endurance - 100K Program/Erase Cycles Minimum * Extended Temperature : -25C ~ 85C * Support Common Flash Memory Interface * Output Driver Control by Configuration Register * Low Vcc Write Inhibit * Package : TBD
The K8A(56/57)15E featuring single 1.8V power supply is a 256Mbit Burst Multi Bank Flash Memory organized as 16Mx16. The memory architecture of the device is designed to divide its memory arrays into 256 blocks(Uniform block part)/259 blocks(Boot block part) with independent hardware protection. This block architecture provides highly flexible erase and program capability. The K8A(56/57)15E NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Regarding read access time, the K8A5615E provides an 11ns burst access time and an 95ns initial access time at 66MHz. At 83MHz, the K8A5615E provides an 9ns burst access time and an 95ns initial access time. At 108MHz, the K8A5715E provides an 7ns burst access time and an 95ns initial access time. At 133MHz, the K8A5715E provides an 6ns burst access time and an 95ns initial access time. The device performs a program operation in units of 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.6sec. The device requires 25mA as program/erase current in the extended temperature ranges. The K8A(56/57)15E NOR Flash Memory is created by using Samsung's advanced CMOS process technology.
3.0 PIN DESCRIPTION
Pin Name A0 - A23 DQ0 - DQ15 CE OE RESET VPP WE WP CLK RDY AVD DPD Vcc VSS Pin Function Address Inputs Data input/output Chip Enable Output Enable Hardware Reset Pin Accelerates Programming Write Enable Hardware Write Protection Input Clock Ready Output Address Valid Input Deep Power Down Power Supply Ground
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
TBD
Rev. 1.0
4.0 BALL FBGA TOP VIEW (BALL DOWN)
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Bank 0 Address X Dec Bank 0 Cell Array
Rev. 1.0
5.0 FUNCTIONAL BLOCK DIAGRAM
Vcc Vss Vpp CLK CE OE WE WP RESET RDY AVD DPD I/O Interface & Bank Control Bank 1 Address X Dec
Latch & Control
Y Dec
Y Dec
Bank 1 Cell Array
Latch & Control
Bank 15 Address
X Dec
Bank 15 Cell Array
Y Dec
Erase Control Block Inform Program Control
Latch & Control
A0~A23 DQ0~ DQ15
High Voltage Gen.
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
K8 A 56 15 E T C - S E 1E
Rev. 1.0
6.0 ORDERING INFORMATION
Samsung NOR Flash Memory Access Time 1E : Refer to Table 1 Operating Temperature Range C : Commercial Temp. (0 C to 70 C) E : Extended Temp. (-25 C to 85 C) Package F : FBGA D : FBGA(Lead Free) S : FBGA(Lead Free, OSP) Version C : 4th Generation Block Architecture T : Top Boot Block, B : Bottom Boot Block Z : Uniform Block
Device Type A : De-Multiplexed Burst Density(*Note) 54 : 256Mbits for 66/83MHz(Sync MRS) 55 : 256Mbits for 108/133MHz(Sync MRS) 56 : 256Mbits for 66/83MHz(No option) 57 : 256Mbits for 108/133MHz(No option) Organization 15 : x16 Organization Operating Voltage Range E : 1.7 V to 1.95V
NOTE : Density : (1) 54 : 256Mb for 66/83Mhz with the Sync MRS option (2) 55 : 256Mb for 108/133Mhz with the Sync MRS option (3) 56 : 256Mb for 66/83Mhz with no option (4) 57 : 256Mb for 108/133Mhz with no option
[Table 1] PRODUCT LINE-UP K8A(56/57)15E Mode Synchronous/ Burst VCC=1.7V -1.95V Asynchronous Speed Option Max. Initial Access Time (tIAA, ns) Max. Burst Access Time (tBA, ns) Max. Access Time (tAA, ns) Max. CE Access Time (tCE, ns) Max. OE Access Time (tOE, ns) 1C (66MHz) 95 11 100 100 15 1D (83MHz) 95 9 100 100 15 1E (108MHz) 95 7 100 100 15 1F (133MHz) 95 6 100 100 15
[Table 2] PRODUCT Classification Speed/Boot Option 256Mb for 66/83MHz 256Mb for 108/133MHz Top K8A5615ETC K8A5715ETC Bottom K8A5615EBC K8A5715EBC Uniform K8A5615EZC K8A5715EZC
[Table 3] K8A(56/57)15E DEVICE BANK DIVISIONS Bank 0 ~ Bank 15 Mbit 256Mbit (Boot block part) 256Mbit (Uniform block part) Block Sizes Four 16Kword blocks and two hundred fifty-five 64Kword blocks Two hundred fifty-six 64Kword blocks
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Bank size 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb Quantity of Blocks 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Block Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords
Rev. 1.0
[Table 4] K8A(56/57)15EZC DEVICE BANK DIVISIONS (Uniform block) Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
[Table 5] K8A(56/57)15ETC DEVICE BANK DIVISIONS (Top Boot block) Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bank size 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb Quantity of Blocks 4 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Block Size 16 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Bank size 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb Quantity of Blocks 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 15 4 Block Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 16 Kwords
Rev. 1.0
[Table 6] K8A(56/57)15EBC DEVICE BANK DIVISIONS (Bottom Boot block) Bank 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
7.0 PRODUCT INTRODUCTION
The K8A(56/57)15E is 256Mbit (268,435,456 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 256 blocks (64-Kword x 256 blocks, Uniform block part) / 259 blocks (16-Kword x 4 + 64-Kword x 255, Boot block part). Programming is done in units of 16 bits (Word). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 256 / 259 memory blocks can be hardware protected. Regarding read access time, the K8A5615E provides 11ns burst access time and 95ns initial access time at 66MHz. At the K8A5615E provides 9ns burst access time and 95ns initial access time at 83MHz. At the K8A5715E provides 7ns burst access time and 95ns initial access time at 108MHz. At 133MHz, the K8A5715E provides 6ns burst access time and 95ns initial access time. The command set of K8A(56/57)15E is compatible with standard Flash devices. The device uses Chip Enable (CE), Write Enable (WE), Output Enable (OE) to control asynchronous read and write operation. For burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8A(56/57)15E is implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8A(56/57)15E has means to indicate the status of completion of program/erase operations. The status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The device requires only 35mA as burst and asynchronous mode read current and 25 mA for program/erase operations.
[Table 7] Device Bus Operations Operation Asynchronous Read Operation Write Standby Hardware Reset Load Initial Burst Address CE L L H X L L H X L OE L H X X H L X X H X X H H X X H WE H A0-23 Add In Add In X X Add In X X X Add In DQ0-15 I/O I/O High-Z High-Z X Burst DOUT High-Z High-Z I/O RESET H H H L H H H L H X X H X X CLK L L X X AVD L X X X
Burst Read Operation Terminate Burst Read Cycle Terminate Burst Read Cycle via RESET Terminate Current Burst Read Cycle and Start New Burst Read Cycle
NOTE : L=VIL (Low), H=VIH (High), X=Don't Care.
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
8.0 COMMAND DEFINITIONS
The K8A(56/57)15E operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 8. [Table 8] Command Sequences Command Definitions Asynchronous Read Reset 5),20) Autoselect Manufacturer ID Autoselect Device ID 6) Autoselect Block Protection Verify 7) Autoselect Handshaking Program Unlock Bypass Unlock Bypass Program9) Unlock Bypass Block Erase 9) Unlock Bypass Chip Erase 9) Unlock Bypass Reset Chip Erase Block Erase Erase Suspend 10) Erase Resume
11) 6), 8) 6)
Cycle Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data 1 1 4 4 4 4 4 3 2 2 2 2 6 6 1 1 1 1 3 1
1st Cycle RA RD XXXH F0H 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH 555H AAH XXX A0H XXX 80H XXXH 80H XXXH 90H 555H AAH 555H AAH (DA)XXXH B0H (DA)XXXH 30H (DA)XXXH B0H (DA)XXXH 30H XXX 60H (DA)X55H 98H
2nd Cycle 3rd Cycle
4th Cycle
5th Cycle
6th Cycle
2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H PA PD BA 30H XXXH 10H XXXH 00H 2AAH 55H 2AAH 55H
(DA)555H 90H (DA)555H 90H (BA)555H 90H (DA)555H 90H 555H A0H 555H 20H
(DA)X00H ECH (DA)X01H Note6 (BA)X02H 00H / 01H (DA)X03H 0H/1H PA PD
555H 80H 555H 80H
555H AAH 555H AAH
2AAH 55H 2AAH 55H
555H 10H BA 30H
Program Suspend 12) Program Resume 11) Block Protection/Unprotection 13) CFI Query 14)
XXX 60H
ABP 60H
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Cycle Add Data Add Data Add Data
17),18)
Rev. 1.0
Command Definitions Write to Buffer 15) Program buffer to Flash 15) Write to Buffer Abort Reset 16),19) Set Burst Mode Configuration Register Enter OTP Block Region Exit OTP Block Region
NOTE :
1st Cycle 555H AAH BA 29H 555H AAH 555H AAH 555H AAH 555H AAH
2nd Cycle 2AAH 55H
3rd Cycle BA 25H
4th Cycle BA WC
5th Cycle PA PD
6th Cycle WBL PD
3 1 3 3 3 4
2AAH 55H 2AAH 55H 2AAH 55H 2AAH 55H
XXX F0H Note 18 C0H XXX 70H 555H 75H XXX 00H
Add Data Add Data Add Data
1) RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A23 ~ A14), DA : Bank Address (A23 ~ A20) ABP : Address of the block to be protected or unprotected , CR : Configuration Register Setting WBL : Write Buffer Location, WC : Word Count 2) The 4th cycle data of autoselect mode and RD are output data. The others are input data. 3) Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD and Device ID. 4) Unless otherwise noted, address bits A23-A11 are don't cares. 5) The reset command is required to return to read mode. If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode. If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode. If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that bank was in erase suspend mode. 6) The 3rd and 4th cycle bank address of autoselect mode must be same. Device ID Data : "2206H" for Top Boot Block Device, "2207H" for Bottom Boot Block Device, "301BH" for Uniform Block Device 7) Normal Block Protection Verify : 00H for an unprotected block and 01H for a protected block. OTP Block Protect verify (with OTP Block Address after Entering OTP Block) : 00H for unlocked, and 01H for locked. 8) 0H for handshaking, 1H for non-handshaking 9) The unlock bypass command sequence is required prior to this command sequence. 10) The system may read and program in non-erasing blocks when in the erase suspend mode. The system may enter the autoselect mode when in the erase suspend mode. The erase suspend command is valid only during a block erase operation, and requires the bank address. 11) The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address. 12) This mode is used only to enable Data Read by suspending the Program operation. 13) Set ABP(Address of the block to be protected or unprotected) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH and A0 = VIL for protected. 14) Command is valid when the device is in Read mode or Autoselect mode. 15) For Buffer Program, Firstly Enter "Write to Buffer" Command sequence and then Enter Block Address and Word Count which is the number of word data will be programmed. Word Count is smaller than the number of data wanted to program by one, Example if 15 words are wanted to program then WC (Word Count) is 14. After Entering Command, Enter PA/PD's (Program Addresses/ Program Data). Finally Enter "Program buffer to Flash" Command sequence, This starts a buffer program operation. This Device supports 32-word Buffer Program. There is some caution points. - The number of PA/PD's which are entered must be same to WC+1 - PA's which are entered must be same A23~A5 address bits because Buffer Address is A23~A5 address and decided by PA entered firstly. - If PA which are entered isn't same Buffer Address, then PA/PD which is entered may be ignored and this buffer programming operation is aborted. To return to normal operation, hardware reset or "Write to Buffer Abort Reset" command is issued. - Overwrite for program buffer is also prohibited. 16) Command sequence resets device for next command after aborted write-to-buffer operation. 17) See "Set Burst Mode Configuration Register" for details. 18) On the third cycle, the data should be "C0h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched. 19) After software reset and write to buffer abort reset command, min. 5us recovery time is needed for normal read mode.
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
9.0 DEVICE OPERATION
The device has inputs/outputs that accept both address and data information. To write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the system must drive CLK, WE and CE to VIL and OE to VIH when writing commands or data. The device provides the unlock bypass mode to save its program time for program operation. Unlike the standard program command sequence which is comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the entire device can be erased. Table 16 indicates the address space that each block occupies. The device's address space is divided into sixteen banks. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "block address" is the address bits required to uniquely select a block. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
9.1 Read Mode
The device automatically enters to asynchronous read mode after device power-up. For synchronous read, the device needs to be set mode register prior to read operation. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset command is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase operation, or if the bank is in the autoselect mode. (1) K8A5415ET(B)(Z)C : 66/83Mhz with the Sync MRS option (2) K8A5515ET(B)(Z)C : 108/133Mhz with the Sync MRS option The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Burst Mode Configuration Register Setting to A19=1. If several CLKs exist in AVD low, the last rising edge is valid CLK. (3) K8A5615ET(B)(Z)C : 66/83Mhz with no option (4) K8A5715ET(B)(Z)C : 108/133Mhz with no option The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low. If several CLKs exist in AVD low, the last rising edge is valid CLK.
9.1.1 Asynchronous Read Mode
For the asynchronous read mode a valid address should be asserted on A0-A23, while driving AVD and CE to VIL. WE should remain at VIH. The data will appear on DQ0-DQ15. Since the memory array is divided into sixteen banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. To prevent the memory content from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset.
9.1.1.1 Asynchronous Page Read Mode
16-Words Page mode is supported for fast asynchronous read. After address access time(tAA), sixteen data words are loaded into an internal page buffer. A0~A3 bits determine which page word is output during a read operation. A4~A23 and AVD must be stable throughout the page read access. Figure 11 shows the Asynchronous Page Read Mode timing.
9.1.2 Synchronous (Burst) Read Mode
The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the system should determine how many clock cycles are desired for the initial word(tIAA) of each burst access and what mode of burst operation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be read during burst read mode by using AVD signal with a bank address which is programming or erasing. To initiate the synchronous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation.
9.1.2.1 Continuous Linear Burst Read
(1) K8A5415ET(B)(Z)C : 66/83Mhz with the Sync MRS option (2) K8A5515ET(B)(Z)C : 108/133Mhz with the Sync MRS option The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Burst Mode Configuration Register Setting to A19=1. If several CLKs exist in AVD low, the last rising edge is valid CLK. (3) K8A5615ET(B)(Z)C : 66/83Mhz with no option (4) K8A5715ET(B)(Z)C : 108/133Mhz with no option The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low. If several CLKs exist in AVD low, the last rising edge is valid CLK. The initial word is output tIAA after the rising edge of the last CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
cycle, which automatically increase the internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is crossing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of additional clock cycle can vary from zero to thirteen cycles, and the exact number of additional clock cycle depends on the starting address of burst read. The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential burst data, wrapping around to address 0000000h after it reaches the highest addressable memory location until the system asserts CE high, RESET low or AVD low in conjunction with a new address.(Refer to Table 7.) The reset command does not terminate the burst read operation. When it accesses the bank is programming or erasing, continuous burst read mode will output status data. And status data will be sustained until the system asserts CE high or RESET low or AVD low in conjuction with a new address. Note that at least 10ns is needed to start next burst read operation from terminating previous burst read operation in the case of asserting CE high. 8-, 16-Word Linear Burst Read As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap, in which a fixed number of words are read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode. (Refer to Table 9) [Table 9] Burst Address Groups(Wrap mode) Burst Mode 8 word 16 word Group Size 8 words 16 words Group Address Ranges 0-7h, 8-Fh, 10-17h, .... 0-Fh, 10-1Fh, 20-2Fh, ....
As an example: In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar manner, 16-word wrap mode begins its burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group.
9.2 Programmable Wait State
The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven from low to high for burst read mode. Upon power up, the number of total initial access cycles defaults to fourteen.
9.3 Handshaking
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configuration.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE goes low indicates the initial word of valid burst data.(RDY can be low active by Extended configuration register A11 settng : RDY low indicates data valid) Using the autoselect command sequence, the handshaking feature will be verified in the device.
9.4 Set Burst Mode Configuration Register
The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The burst mode configuration register must be set before the device enters burst mode. The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h, address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched. The device returns to default setting after power up or hardware reset.
9.4.1 Programmable Wait State Configuration
This feature informs the device the number of clock cycles that must elapse after AVD is driven from low to high before data will be available. This value is determined by the input frequency of the device. Address bits A14-A11 determine the setting. (See Configuration Register Table 10.) The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst mode. Note that hardware reset will revert the wait state to the default setting, that is 14 initial cycles.
9.4.2 Burst Read Mode Setting
The device supports three different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap.
9.4.3 RDY Configuration
By default, the RDY pin will be high whenever there is valid data on the output. (RDY can be low active by configuration register A11 settng : RDY low indicates data valid) The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting. The RDY pin behaves same way in word boundary crossing case.
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Settings(Binary) 1 = Synchronous Burst Read Mode 0 = Asynchronous Read Mode (default) 1 = RDY active one clock cycle before data 0 = RDY active with data(default) 000 = Continuous(default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011~111 = Reserve
Rev. 1.0
[Table 10] Burst Mode Configuration Register Table : K8A54(55)15ET(B)(Z)C : 66/83/108/133Mhz with the Sync MRS option Address Bit A19 A18 A17 A16 A15 A14 A13 A12 Programmable Wait State A11 Burst Read Mode Function Read Mode RDY Active
0000 = Data is valid on the 4th active CLK edge after AVD transition to VIH 0001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (40Mhz*) 0010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (50/54Mhz*) 0011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (60/66Mhz*) 0100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (70Mhz*) 0101 = Data is valid on the 9th active CLK edge after AVD transition to VIH (80/83Mhz*) 0110 = Data is valid on the 10th active CLK edge after AVD transition to VIH (90/100Mhz*) 0111 = Data is valid on the 11th active CLK edge after AVD transition to VIH (108/110Mhz*) 1000 = Data is valid on the 12th active CLK edge after AVD transition to VIH (120Mhz*) 1001 = Data is valid on the 13th active CLK edge after AVD transition to VIH (133Mhz*,default) 1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH 1011 = Data is valid on the 15th active CLK edge after AVD transition to VIH
NOTE : Initial wait state should be set according to it's clock frequency. Table 10 recommend the program wait state for each clock frequencies. Not 100% tested
[Table 11] Burst Mode Configuration Register Table : K8A56(57)15ET(B)(Z)C : 66/83/108/133Mhz with no option Address Bit A18 A17 A16 A15 A14 A13 A12 Programmable Wait State A11 Burst Read Mode Function RDY Active Settings(Binary) 1 = RDY active one clock cycle before data 0 = RDY active with data(default) 000 = Continuous(default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011~111 = Reserve 0000 = Data is valid on the 4th active CLK edge after AVD transition to VIH 0001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (40Mhz*) 0010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (50/54Mhz*) 0011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (60/66Mhz*) 0100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (70Mhz*) 0101 = Data is valid on the 9th active CLK edge after AVD transition to VIH (80/83Mhz*) 0110 = Data is valid on the 10th active CLK edge after AVD transition to VIH (90/100Mhz*) 0111 = Data is valid on the 11th active CLK edge after AVD transition to VIH (108/110Mhz*) 1000 = Data is valid on the 12th active CLK edge after AVD transition to VIH (120Mhz*) 1001 = Data is valid on the 13th active CLK edge after AVD transition to VIH (133Mhz*,default) 1010 = Data is valid on the 14th active CLK edge after AVD transition to VIH 1011 = Data is valid on the 15th active CLK edge after AVD transition to VIH
[Table 12] Burst Address Sequences Start Addr. 0 1 Wrap 2 . . Burst Address Sequence Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... . . 8-word Burst 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 . . 16-word Burst 0-1-2-3 ... -D-E-F 1-2-3-4 ... -E-F-0 2-3-4-5 ... -F-0-1 . .
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
9.5 Autoselect Mode
By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory array). Standard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection. Table 13 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write Reset command(F0H) into the command register. [Table 13] Autoselect Mode Description Description Manufacturer ID Device ID Block Protection/Unprotection Handshaking Address (DA) + 00H (DA) + 01H (BA) + 02H (DA) + 03H Read Data ECH 2206H (Top Boot Block), 2207H (Bottom Boot Block), 301BH (Uniform Block) 01H (protected), 00H (unprotected) 0H : handshaking, 1H : non-handshaking
9.6 Standby Mode
When the CE inputs is held at VCC 0.2V, and the system is not reading or writing, the device enters Stand-by mode to minimize the power consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE input. When the device is in either of these standby modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC5 in the DC Characteristics table represents the standby current specification.
9.7 Automatic Sleep Mode
The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses remain stable for tAA+60ns, the device automatically enables this mode. The Automatic sleep mode is depends on the CE, WE and OE signal, so CE, WE and OE signals are held at any state. In a sleep mode, output data is latched and always available to the system. When OE is active, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current.
9.8 Output Disable Mode
When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.
9.9 Block Protection & Unprotection
To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are don't care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command). The device offers three types of data protection at the block level: * The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block. * When WP is at VIL, the two outermost blocks are protected.(Boot block part : K8A(54/55/56/57)15ET(B)C) * When WP is at VIL, the last one block (BA255) is protected.(Uniform block part :K8A(54/55/56/57)15EZC) * When VPP is at VIL, all blocks are protected. Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.
9.10 Hardware Reset
The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET pulse.
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asynchronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 12 for the timing diagram. When RESET is at logic high, the device is in standard operation. When RESET transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.
9.11 Software Reset
The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in Don't Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an program command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend)
9.12 Program
The K8A(56/57)E can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location.
9.13 Accelerated Program
The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. In accelerated program mode, the system would use a two-cycle program command sequence for only a word program. By removing VID returns the device to normal operation mode. Note that Read While Accelerated Program(Erase) and Program suspend(Erase suspend) mode are not guaranteed. * Program/Erase cycling must be limited below 100cycles for optimum performance. * Ambient temperature requirements : TA = 30C10C
9.14 Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 32-word in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi-ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the block address in which programming will occur. The fourth cycle writes the block address and the number of word locations, minus one, to be programmed. For example, if the system will program 19 unique address locations, then 12h should be written to the device. This tells the device how many write buffer addresses will be loaded with data. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A23(max.) ~ A5 entered at fifth cycle. All subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit A23(max.) ~ A5 as those entered at fifth cycle. Write buffer locations may be loaded in any order. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" com mand at the block address. Any other command address/data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/ resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. Note also that an address loaction cannot be loaded more than once into the write-buffer-page. The Write Buffer Programming Sequence can be aborted in the following ways: * Loading a value that is greater than the buffer size(32-word) during then number of word locations to Program step. (In case, WC > 1FH @Table 8) * The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@ Table 8)
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
* Writing a Program address to have a different write-buffer-page with selected write-buffer-page ( Address bits A23(max) ~ A5 are different) * Writing non-exact "Program Buffer to Flash" command The abort condition is indicated by DQ1 = 1, DQ7 = DATA (for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-to-Buffer-Abort Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. And from the third cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Programming features in Unlock Bypass mode. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
9.15 Accelerated Write Buffer Programming
The device provides accelerated Write Buffer Program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. In accelerated Write Buffer Program mode, the system must enter "Write to Buffer" and "Program Buffer to Flash" command sequence to be same as them of normal Write Buffer Programming. Note that the third cycle of "Write to Buffer Abort Reset" command sequence is required in an accelerated mode. Note that Read While Accelerated Write Buffer Program and Program suspend mode are not guaranteed. * Program/Erase cycling must be limited below 100cycles for optimum performance. * Ambient temperature requirements : TA = 30C10C
9.16 Chip Erase
To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
9.17 Block Erase
To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. Multiple blocks can be erased sequentially by writing the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase operation.
9.18 Unlock Bypass
The K8A(56/57)E provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase, chip erase, write to buffer and write to buffer abort reset operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four bus cycles, the unlock bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always connected with VIH, VIL or VID.).
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
9.19 Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is possible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 30us(recovery time) to suspend the erase operation. Therefore system must wait for 30us(recovery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data immediately from a bank which don't include the block being erased without recovery time(max. 30us) after Erase Suspend command. And, after the maximum 30us recovery time, the device is availble for programming data in a block that is not being erased. But, when the Erase Suspend command is written during the block erase time window (50us), the device terminates the block erase time window and suspends the erase operation in about 2us. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in the bank address which is operating in Erase Suspend or Erase Resume. While erase can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend.
9.20 Program Suspend / Resume
The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 10us is needed to enter the Program Suspend Read mode. Therefore system must wait for 10us(recovery time) to read the data from the bank which include the block being programmed. Otherwise, system can read the data immediately from a bank which don't include block being programmed without recovery time(max. 10us) after Program Suspend command. Like an Erase Suspend mode, the device can be returned to Program mode by using a Program Resume command. In the program suspend mode, protect/unprotect command is prohibited. While program can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend.
9.21 Read While Write Operation
The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write operation. An erase operation may also be suspended to read from or program to another location within the same bank(except the block being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write current specifications.
9.22 OTP Block Region
The OTP Block feature provides a 512-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that block in any manner they choose. The customer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked state or a "1" for Locked state. The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 8). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (FFFE00h~FFFFFFh : Top Boot block device/Uniform block device, 000000h-0001FFh : Bottom Boot block device) normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled. Customer Lockable In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP Block" Command sequence, and then the "Block Protection" Command seqeunce (Table 8) with an OTP Block address. The Locking operation has to be above 100us. "Exit OTP Block" commnad sequence and Hardware reset makes locking operation finished and then exiting from OTP Block after 30us. The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block space can be modified in any way. Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operations. After entering OTP block, program/erase operation on main blocks is prohibited. Enter OTP block command is not allowed while other operation is excuting.
9.23 Low VCC Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO.
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
9.24 Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle.
9.25 Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one
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K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
10.0 FLASH MEMORY STATUS FLAGS
The K8A(56/57)E has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being executed internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins. The status data can be read during burst read mode by using AVD signal with a bank address. That means status read is supported in synchronous mode. If status read is performed, the data provided in the burst read is identical to the data in the initial access. To initiate the synchronous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3, DQ2 and DQ1. [Table 14] Hardware Sequence Flags Status Programming Block Erase or Chip Erase Erase Suspend Read Erase Suspend Read In Progress Erase Suspend Program Program Suspend Read Program Suspend Read Exceeded Time Limits Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block Program Suspended Block Non- program Suspended Block DQ7 DQ7 0 1 Data DQ7 DQ7 Data DQ7 0 DQ7 DQ7 DQ7 DQ7 DQ6 Toggle Toggle 1 Data Toggle 1 Data Toggle Toggle Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 0 Data 1 1 1 0 1 0 DQ3 0 1 0 Data 0 0 Data 0 1 0 0 0 0 DQ2 1 Toggle Toggle 1) Data 1 Toggle 1) Data No Toggle NOTE2 No Toggle No Toggle No Toggle No Toggle DQ1 0 0 0 Data 0 0 Data 0 0 0 0 0 1
Programming Block Erase or Chip Erase Erase Suspend Program Write-toBuffer3) BUSY state Exceeded Timing Limits ABORT State
NOTE : 1) DQ2 will toggle when the device performs successive read operations from the erase/program suspended block. 2) If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle. 3) Note that DQ7 during Write-to-Buffer-Programming indicates the data-bar for DQ7 data for the last loaded write-buffer address location.
DQ7 : Data Polling
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the block being erased or bank contains the block, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 2us and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 2us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block. #OE or #CE should be toggled in each toggle bit status read.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional
- 22 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles if the bank including an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or non-programmed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. #OE or #CE should be toggled in each toggle bit status read.
DQ1 : Buffer Program Abort Indicator
DQ1 indocates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-BufferAbort-Reset command sequence to return the device to reading array data.
RDY: Ready
Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.
Start Read(DQ0~DQ7) Valid Address Read(DQ0~DQ7) Valid Address
Start Read(DQ0~DQ7) Valid Address
DQ7 = Data ?
No No
Yes
DQ6 = Toggle ?
Yes No
No
DQ5 = 1 ?
Yes
DQ5 = 1 ?
Yes
Read(DQ0~DQ7) Valid Address
Yes
Read twice(DQ0~DQ7) Valid Address
No
DQ7 = Data ?
No
DQ6 = Toggle ?
Yes
Fail Figure 1: Data Polling Algorithms
Pass
Fail Figure 2: Toggle Bit Algorithms
Pass
- 23 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
11.0 DEEP POWER DOWN
In order to reduce the power consumption of the device, it shall a deep power down mode inplemented on a seperate pin. The deep power down mode is active when the deep power down signal is activated, high state. In deep power down the device shall turn off all circuitry in order to reach a power consumption of 2uA(tpy). The device shall exit the deep power down mode within 75us after that the deep power down signal has been de-activated, set to low. In deep power down the state of the device chip select shall have no impact on the device power consumption. All programming capabilities of the device are inhibited. At the power up, the device shall accept any order of activation of the reset and deep power down signal. The device shall respond within the specified time for the signal that was deactivated/activated latest. The deep power down mode is activated when DPD pin high state only. If DPD is asserted during a program or erase operation, the device requires a time of tDP(During Internal Routines) before the device is ready to enter DPD mode. Note that user never float the DPD that is, DPD is always connected with VIH, VIL.Deep Power Down (DPD) Parameter DPD Pin High(NOT During Internal Routines) to DPD Mode* DPD Pin High(During Internal Routines) to DPD Mode* DPD Low Time Before Read*
NOTE : Not 100% tested.
Symbol tDP tDP twkup
All Speed Options Min 100 20 75 Typ Max -
Unit ns s s
SWITCHING WAVEFORMS
CE, OE twkup DPD tDP DPD Timings NOT during Internal Routines
CE, OE
twkup
DPD tDP
DPD Timings during Internal Routines Figure 3: DPD Timings
- 24 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
12.0 COMMON FLASH MEMORY INTERFACE
Common Flash Memory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H , the device enters the CFI mode. And then if the system writes the address shown in Table 15, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command. [Table 15] Common Flash Memory Interface Code Description Addresses (Word Mode) 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0017H 0019H
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp(Acceleration Program) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Vpp(Acceleration Program) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Typical timeout per single word write 2N us Typical timeout for Max buffer write 2N us(00H = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2 ms(00H = not supported)
N
1DH
0085H
1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H
0095H 0008H 0009H 000AH 0012H 0001H 0001H 0004H 0000H 0019H 0000H 0000H 0006H 0000H 0002H 0003H 0000H 0080H 0000H
Max. timeout for word write 2 times typical
N
Max. timeout for buffer write 2 times typical
N
Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2 times typical(00H = not supported)
N
Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device (Note 1) Erase Block Region 1 Information (Boot block part : (K8A(56/57)15ET(B)C) ) Bits 0~15: y+1=block number Bits 16~31: block size= z x 256bytes
- 25 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Description Addresses (Word Mode) 2DH 2EH 2FH 30H 31H 32H 33H 34H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 40H 41H 42H 43H 44H 45H Data 00FFH 0000H 0000H 0002H 00FEH 0000H 0000H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0050H 0052H 0049H 0030H 0030H 0000H
Rev. 1.0
Erase Block Region 1 Information (Uniform block part : (K8A(56/57)15EZC) ) Bits 0~15: y+1=block number Bits 16~31: block size= z x 256bytes
Erase Block Region 2 Information (Boot block part : (K8A(56/57)15ET(B)C) )
Erase Block Region 2 Information (Uniform block part : (K8A(56/57)15EZC) )
Erase Block Region 3 Information
Erase Block Region 4 Information
Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 00 = Not Supported, 01 = Supported Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 03 = 16 Word Page Top/Bottom Boot/Uniform Block Flag 02H = Bottom Boot Device, 03H = Top Boot Device, 04H = Uniform Device Max. Operating Clock Frequency (MHz ) (Note 2) RWW(Read While Write) Functionality Restriction (00H = non exists , 01H = exists) Handshaking 00 = Not Supported at both mode, 01 = Supported at Sync. Mode 10 = Supported at Async. Mode, 11 = Supported at both Mode
46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H
0002H 0001H 0000H 0001H 0001H 0001H 0003H 0003H 0085H 0000H 0001H
NOTE : 1) Uniform block part (K8A(56/57)15EZC) : Data is 01H Boot block part (K8A(56/57)15ET(B)C) : Data is 02H 2) Max. Operating Clock Frequency : Data is 85H in 108/133Mhz part (K8A5715E(T/B/Z)C), Data is 53H in 66/83Mhz part (K8A5615E(T/B/Z)C)
- 26 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Symbol Vcc Vcc VIN Tstg IOS TA (Commercial Temp.) TA (Extended Temp.) VPP All Other Pins Rating -0.5 to +2.5 -0.5 to +9.5 -0.5 to +2.5 -65 to +100 5 0 to +70 -25 to + 85 C mA C C V Unit
Rev. 1.0
13.0 ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Storage Temperature Short Circuit Output Current Operating Temperature
NOTE : 1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns. 2) Minimum DC input voltage is -0.5V on VPP . During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC input voltage is +9.5V on VPP which, during transitions, may overshoot to +12.0V for periods <20ns. 3) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
14.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )
Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 1.7 0 Typ. 1.8 0 Max 1.95 0 Unit V V
NOTE : 1) Data retention is not guaranteed on Operating condition Extended temperature(-25'C~85'C) over.
- 27 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Symbol ILI ILIP ILO ICCB1 ICC1 Test Conditions VIN=VSS to VCC, VCC=VCCmax VCC=VCCmax , VPP=VCCmax VCC=VCCmax , VPP=9.5V VOUT=VSS to VCC, VCC=VCCmax, OE=VIH CE=VIL, OE=VIH (@133MHz) CE=VIL, OE=VIH CE=VIL, OE=VIH, WE=VIL, VPP=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH , VPP=9.5V CE= RESET=VCC 0.2V RESET = VSS 0.2V CE=VSS 0.2V, Other Pins=VIL or VIH VIL = VSS 0.2V, VIH = VCC 0.2V 10MHz Min - 1.0 - 1.0 - 1.0 -0.5 VCC-0.4 IOL = 100 A , VCC=VCCmin IOH = -100 A , VCC=VCCmin VCC-0.1 8.5 Vpp = 9.5V Vpp = 1.95V Typ 35 35 25 45 20 30 30 30 2 9.0 0.8 Max + 1.0 + 1.0 35 + 1.0 55 55 40 70 30 120 120 120 20 0.4 VCC+0.4 0.1 9.5 1.4 5 50
Rev. 1.0
15.0 DC CHARACTERISTICS
Parameter Input Leakage Current VPP Leakage Current Output Leakage Current Active Burst Read Current Active Asynchronous Read Current Active Write Current
2)
Unit A A A A mA mA mA mA mA A A A A V V V V V V mA A
ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 VIL VIH VOL VOH VID VLKO Ivpp
Read While Write Current Accelerated Program Current Standby Current Standby Current During Reset Automatic Sleep Mode 3) Deep Power Down Mode Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage Vpp current in program/erase
NOTE : 1) Maximum ICC specifications are tested with VCC = VCCmax. 2) ICC active while Internal Erase or Internal Program is in progress. 3) Device enters automatic sleep mode when addresses are stable for tAA + 60ns.
- 28 -
K8A56(57)15ET(B)(Z)C
Vcc Power-up
Parameter Vcc Setup Time Time between RESET (high) and CE (low)
NOTE: Not 100% tested.
datasheet NOR FLASH MEMORY
Symbol tVCS tRH All Speed Options Min 200 200 Max -
Rev. 1.0
Unit s ns
SWITCHING WAVEFORMS
tVCS tVCCmin
Vcc/Vccq
RESET CE DPD Low
VIH tRH
Figure 4: Vcc Power-up Diagram
NOTE : DPD should be low during power-up sequence.
16.0 CAPACITANCE (TA = 25 C, VCC = 1.8V, f = 1.0MHz)
Item Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Condition VIN=0V VOUT=0V VIN=0V Min Max 10 10 10 Unit pF pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
17.0 AC TEST CONDITION
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Address to Address Skew Value 0V to VCC 3ns(max)@66Mhz, 2.5ns(max)@83Mhz, 1.5ns(max)@108Mhz, 1ns(max)@133Mhz VCC/2 CL = 30pF 3ns(max)
VCC
VCC/2 Input & Output Test Point VCC/2
Device Under Test
0V Input Pulse and Test Point (including CLK characterization)
* CL = 30pF including scope and Jig capacitance Output Load
- 29 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
1B (54 MHz) Min Max 95 14.5 14.5 9 9 14.5 14.5 0.6x tCLK 3 5 2 0 5 7 4 6 4 18.5 0.4x tCLK 1C (66 MHz) Min 5 2 0 5 6 3 6 3 15.1 0.4x tCLK Max 95 11 11 9 9 11 11 0.6x tCLK 3 1D (83 MHz) Min 4 2 0 4 5 3 4.5 3 12.05 0.4x tCLK Max 95 9 9 9 9 9 9 0.6x tCLK 2.5 1E (108 MHz) Min 3.5 2 0 3.5 2 2 4 2 9.26 0.4x tCLK Max 95 7 7 9 9 7 7 0.6x tCLK 1.5 1F (133 MHz) Min 2.5 2 0 2.5 2 2 3.5 2 7.52 0.4x tCLK Max 95 6 6 9 9 6 6 0.6x tCLK 1
Rev. 1.0
18.0 AC CHARACTERISTICS
18.1 Synchronous/Burst Read
Parameter Initial Access Time Burst Access Time Valid Clock to Output Delay AVD Setup Time to CLK AVD Hold Time from CLK AVD High to OE Low Address Setup Time to CLK Address Hold Time from CLK Data Hold Time from Next Clock Cycle Output Enable to RDY valid CE Disable to High Z OE Disable to High Z CE Setup Time to CLK CE Enable to RDY active CLK to RDY Setup Time RDY Setup Time to CLK CLK period CLK High or Low Time CLK Fall or Rise Time Symbol tIAA tBA tAVDS tAVDH tAVDO tACS tACH tBDH tOER tCEZ tOEZ tCES tRDY tRDYA tRDYS tCLK tCLKH/L tCLKHCL Un it ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
- 30 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS
datasheet NOR FLASH MEMORY
7.5ns typ(133MHz). tCEZ

Rev. 1.0
13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 tCES CE
1 2 3 4 5
11
12
13
CLK tAVDS AVD tACS Aa tACH DQ0: DQ15 tAVDS tAVDH

tBDH tBA
A0-A23
Hi-Z Da+n tOEZ
tIAA
Da
Da+1 Da+2 Da+3 Da+4 Da+5 Da+6
OE tRDY RDY Hi-Z tOER
tRDYS tRDYA Figure 5: Continuous Burst Mode Read (133 MHz)
Hi-Z
11 cycles for initial access shown. CR setting : A14=0, A13=1, A12=1, A11=1 tCES CE
11 1 2 3 4 9 10
9.25ns typ(108MHz). tCEZ
CLK
tAVDS AVD tACS Aa tACH DQ0: DQ15 tIAA OE tRDY RDY Hi-Z tOER tAVDS tAVDH
tBDH tBA
A0-A23
Figure 6: Continuous Burst Mode Read (108 MHz)

Hi-Z Da+n
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Da+6 tOEZ
tRDYS tRDYA
Hi-Z
- 31 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS
datasheet NOR FLASH MEMORY
7.5ns typ(133MHz).
Rev. 1.0
13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 tCES CE
1 2 3 4
11
12
13
CLK tAVDS
AVD tACS Aa tACH DQ0: DQ15
tAVDS tAVDH
tBDH tBA
A0-A23
tIAA
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
OE tRDY RDY Hi-Z tOER
Figure 7: 8 word Linear Burst Mode with Wrap Around (133MHz)
13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 tCES CE
1 2 3
7.5ns typ(133MHz).
4 10 111 12 13
tRDYS tRDYA

CLK tAVDS
AVD tACS Aa tACH DQ0: DQ15
tAVDS tAVDH
tBDH tBA
A0-A23
tIAA
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
OE tRDY RDY Hi-Z tOER
Figure 8: 8 word Linear Burst with RDY Set One Cycle Before Data
(Wrap Around Mode, CR setting : A18=1)
tRDYS tRDYA
- 32 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS
datasheet NOR FLASH MEMORY
13 cycles for initial access shown. CR setting : A14=1, A13=0, A12=0, A11=1 7.5ns typ(133MHz). tCEZ
Rev. 1.0
tCES CE
1 2
3
4
5
11
12
13
CLK
tAVDS AVD tACS Aa tACH DQ0: DQ15 tAVDS tAVDH
tBDH

A0-A23
tBA
Hi-Z D6 tOEZ
tIAA
D7
D8
D9
D10
D15
D0
OE tRDY RDY Hi-Z tOER
Figure 9: 16 word Linear Burst Mode with Wrap Around (133Mhz)
tRDYS tRDYA
Hi-Z
18.2 Asynchronous Read
Parameter Access Time from CE Low Asynchronous Access Time Page Address Access Time Output Hold Time from Address, CE or OE AVD Low Setup Time to CE Enable AVD Low Hold Time from CE Enable Output Enable to Output Valid Output Enable Hold Time Output Disable to High Z*
NOTE: Not 100% tested.
Symbol tCE tAA tPA tOH tAVDCS tAVDCH tOE Read
All Speed option Min 3 0 0 0 10 Max 100 100 15 15 9
Unit ns ns ns ns ns ns ns ns ns ns
Toggle and Data Polling
tOEH tOEZ
- 33 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS
Asynchronous Mode Read
CLK CE
VIL
datasheet NOR FLASH MEMORY
Rev. 1.0
tAVDCS AVD tOE OE tOEH WE tCE Valid RD tAA A0-A23 VA Figure 10: Asynchronous Mode Read
tAVDCH
tOEZ
DQ0-DQ15
NOTE : 1) VA=Valid Read Address, RD=Read Data. 2) AVD should be held VIL in asynchronous read mode. 3) Asynchronous mode may not support read following four sequential invalid read condition within 200ns. 4) CLK "HIGH" should be prohibited in asynchronous read mode start (From CE LOW).
- 34 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS Page Read Operations
CLK CE
VIL
datasheet NOR FLASH MEMORY

tAVDCH
Rev. 1.0
tAVDCS AVD tOE OE tOEH WE tCE

tOEZ
DQ0-DQ15 tAA
Da tPA
Db tOH
Dp

A0-A3 A4-A23
Aa
Ab VA
Ac
Ap
Figure 11: Asynchronous Page Mode Read
NOTE: CLK "HIGH" should be prohibited in asynchronous read mode start (From CE LOW).
- 35 -
K8A56(57)15ET(B)(Z)C AC CHARACTERISTICS
Hardware Reset(RESET) Parameter RESET Pin Low(During Internal Routines) to Read Mode (Note) RESET Pin Low(NOT During Internal Routines) to Read Mode (Note) RESET Pulse Width* Reset High Time Before Read (Note)
NOTE : 1) Not 100% tested.
datasheet NOR FLASH MEMORY
Symbol tReady tReady tRP tRH All Speed Options Min 200 200 Max 20 500 -
Rev. 1.0
Unit s ns ns ns
SWITCHING WAVEFORMS
CE, OE tRH RESET tRP tReady Reset Timings NOT during Internal Routines
CE, OE tReady
RESET tRP
Reset Timings during Internal Routines Figure 12: Reset Timings
- 36 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
All Speed Option Min 75 0 30 30 0 0 0 0 30 45 0 500 1 Typ 80 250 89.6 80 1.4 44.8 0.6 Max -
Rev. 1.0
AC CHARACTERISTICS
18.3 Erase/Program Operation
Parameter WE Cycle Time1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE Setup Time CE Hold Time WE Pulse Width WE Pulse Width High Latency Between Read and Write Operations Word Programming Operation Single word Buffer Program 32-word Buffer Program
3) 2) 2)
Symbol tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH tSR/W tPGM tPGM_BP tPGM_BP tACCPGM tACCPGM_BP tACCPGM_BP tBERS tVPP tVPS
Unit ns ns ns ns ns ns ns ns ns ns ns s s s s s s sec ns s
Accelerated Programming Operation Accelerated Single word Buffer Program Accelerated 32-word Buffer Program Block Erase Operation (64KW block) VPP Rise and Fall Time VPP Setup Time (During Accelerated Programming)
3)
NOTE : 1) Not 100% tested. 2) Internal programming algorithm is optimized for Buffer Program, so Normal word programming or Single word Buffer Program use Buffer Program algorithm. 3) Typical 32-word Buffer Program time pays due regard to that Each program data pattern ("11", "10". "01", "00") has a same portion in 32-word Buffer.
- 37 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Limits Min. 64 Kword 16 Kword 64 Kword 16 Kword 5)
Rev. 1.0
18.4 Erase/Program Performance
Parameter Block Erase Time Chip Erase Time
3)
Typ. 0.6 0.3 154.2 0.4 0.2 103 80 2.8 80 1.4 47 23.4
Max. 3.0 1.5 771 3.0 1.5 515 550 14 550 7 235 117
Unit
Comments
sec
Accelerated Block Erase Time (4) Accelerated Chip Erase Time Word Programming Time 32-word Buffer Programming Time Accelerated Word Programming Time
3),4)
Includes 00h programming prior to erasure
-
s / word
Excludes system level overhead
Accelerated 32-word Buffer Programming Time Chip Buffer Programming Time Accelerated Buffer Chip Programming Time
NOTE :
sec
Excludes system level overhead
1) 25C, VCC = 1.8V, 100,000 cycles, typical pattern. 2) System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each word. 3) Chip Erase time & Accel. Chip Erase time for boot block part : K8A(56)(57)15ET(B)C 4) Accelerated Program/Erase cycling must be limited below 100cycles for optimum performance. Ambient temperature requirements : TA = 30C10C 5) Not 100% tested.
SWITCHING WAVEFORMS Program Operations
Program Command Sequence (last two cycles) tAS A0:A23 tAH 555h PA VA VA
Read Status Data
DQ0-DQ15
A0h
PD tDS tDH
In Progress
Complete
CE
OE tWP
tCH
WE tWPH tCS CLK VCC VIL tWC
tPGM
NOTE : 1) PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2) "In progress" and "complete" refer to status of program operation. 3) A16-A23 are don't care during command sequence unlock cycles. 4) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
Figure 13: Program Operation Timing

- 38 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS Buffer Program Operations
Buffer Program Command Sequence
datasheet NOR FLASH MEMORY
Word Count Program Address/Data pairs (WC+1) "Buffer to Flash"
Rev. 1.0
tAS tAH A0:A23 555h 2AAh BA BA PA_0 PA_1 PA_N BA
DQ0: DQ15
AAh tDS
55h
25h
WC
PD_0
PD_1
PD_N
29h
CE

OE tWP
WE tCS CLK VCC
VIL
tWPH tWC

tPGM_BP
NOTE : 1) BA = Block Address, WC = Word Count, PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2) Sequential PA_1, PA_2, ... , PA_N must have same address bits A23(max.) ~ A5 as PA_0 entered firstly 3) The number of Program/Data pairs entered must be same as WC+1 because WC = N. 4) "In progress" and "complete" refer to status of program operation. 5) A16-A23 are don't care during command sequence unlock cycles. 6) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
Figure 14: Buffer Program Operation Timing
- 39 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS
datasheet NOR FLASH MEMORY
Erase Command Sequence (last two cycles)
tAS tAH
Rev. 1.0
Erase Operation
Read Status Data
555h for chip erase BA 10h for chip erase VA VA
A0:A23
2AAh
DQ0-DQ15
55h
30h
tDS tDH
In Progress
Complete
CE
OE
tWP
tCH
WE
tWPH tCS
tBERS
CLK VCC
VIL
tWC
NOTE : 1) BA is the block address for Block Erase. 2) Address bits A16-A23 are don't cares during unlock cycles in the command sequence. 3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
Figure 15: Chlp/Block Erase Operations

- 40 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
SWITCHING WAVEFORMS Unlock Bypass Program Operations(Accelerated Program)
CE
WE
A0:A23
PA
DQ0: DQ15
Don't Care
A0h
Don't Care
PD
Don't Care
OE
tVPS VID
VPP VIL or VIH
tVPP
Unlock Bypass Block Erase Operations
CE WE
A0:A23
BA 555h for chip erase Don't Care 80h Don't Care 10h for chip erase 30h Don't Care
DQ0: DQ15
OE
tVPS VID
VPP VIL or VIH
tVPP
NOTE : 1) VPP can be left high for subsequent programming pulses. 2) Use setup and hold times from conventional program operations. 3) Conventional Program/Erase commands as well as Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp.
Figure 16: Unlock Bypass Operation Timings
- 41 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS Data Polling Operations
tCES CE
datasheet NOR FLASH MEMORY
Rev. 1.0
CLK
tAVDS AVD tAVDH A0-A23 tACS VA tACH DQ0: DQ15 tIAA OE Hi-Z

tRDYS Status Data
VA

Status Data
RDY
NOTE : 1) VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data.
Figure 17: Data Polling Timings (During Internal Routine)
Toggle Bit Operations
tCES CE
CLK
tAVDS AVD tAVDH A0-A23 tACS VA tACH DQ0: DQ15 tIAA OE Hi-Z

tRDYS Status Data
VA

Status Data
RDY
NOTE : 1) VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling.
Figure 18: Toggle Bit Timings(During Internal Routine) - 42 -
K8A56(57)15ET(B)(Z)C SWITCHING WAVEFORMS Read While Write Operations
Last Cycle in Program or Block Erase Command Sequence
datasheet NOR FLASH MEMORY
Read status in same bank and/or array data from other bank Begin another Program or Erase Command Sequences
Rev. 1.0
tWC CE
tRC
tRC
tWC

OE tOE tOEH WE tWPH DQ0: DQ15 tWP tDS PD/30h tSR/W A0-A23 tAA tDH RD
tGHWL
tOEH

RD AAh
PA/BA tAS
RA
RA
555h
AVD tAH
Figure 19: Read While Write Operation
NOTE : Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" and checking the status of the program or erase operation in the "busy" bank.
- 43 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Rev. 1.0
19.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE
The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no additional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. Also, the number of additional clock cycle for the first word boundary can varies from zero to thirteen cycles, and the exact number of additional clock cycle depends on the starting address of burst read and programmable wait state settings. For example, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A<14:11>) is "0011" (which means data is valid on the 7th active CLK edge after AVD transition to Vih), six additional clock cycle is needed. Similarly, if the starting address is 16N+15 (the worst case) and programmable wait state setting(A<14:11>) is "0010" (which means data is valid on the 6th active CLK edge after AVD transition to Vih), five additional clock cycle is needed. Below table shows the starting address vs. additional clock cycles for first word boundary. Starting Address vs. Additional Clock Cycles for first word boundary Srarting Address Group for Burst Read 16N 16N+1 16N+2 16N+3 16N+4 16N+5 16N+6 16N+7 16N+8 16N+9 16N+10 16N+11 16N+12 16N+13 16N+14 16N+15 The Residue of (Address/16) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LSB Bits of Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Additional Clock Cycles for First Word Boundary (note1) A<14:11> "0000" Valid data : 4th CLK 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle A<14:11> "0001" Valid data : 5th CLK 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle A<14:11> "0010" Valid data : 6th CLK 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... A<14:11> "1010" Valid data : 14th CLK 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 cycle 13 cycle
NOTE : Address bit A<14:11> means the programmable wait state on burst mode configuration register. Refer to Table 10.
- 44 -
K8A56(57)15ET(B)(Z)C
Case 1 : Start from "16N" address group
datasheet NOR FLASH MEMORY
CR setting : A14=1, A13=0, A12=1, A11=0
14th rising edge CLK
Rev. 1.0
A0-A23 Data Bus :
Aa

0B
0C
0D
0E
0F
10
11
12
CLK
00
0B
0C
0D
0E
0F
10
11
12
13
AVD
No Additional Cycle for First Word Boundary
CE
tCEZ
OE
tOER

tOEZ
RDY
NOTE : 1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc. 2) Address 000000H is also a boundary crossing. 3) No additional clock cycles are needed except for 1st boundary crossing.
Figure 20: Crossing of first word boundary in burst read mode. Case 2 : Start from "16N+3" address group CR setting : A14=1, A13=0, A12=1, A11=0
14th rising edge CLK
A0-A23 Data Bus : CLK
Aa

0D
0D
0E
0F
10
11
12
13
00
0E
0F
10
11
12
13
14
AVD
Additional 1 Cycle for First Word Boundary
CE
tCEZ
OE
tOER

tOEZ
RDY
NOTE : 1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc. 2) Address 000000H is also a boundary crossing. 3) No additional clock cycles are needed except for 1st boundary crossing.
Figure 21: Crossing of first word boundary in burst read mode.
- 45 -
K8A56(57)15ET(B)(Z)C
Case3 : Start from "16N+4" address group
datasheet NOR FLASH MEMORY
CR setting : A14=1, A13=0, A12=1, A11=0
14th rising edge CLK
Rev. 1.0
A0-A23 Data Bus : CLK
Aa

0E
0F
10
11
12
13
00
0E
0F
10
11
12
13
14
AVD
Additional 2 Cycle for First Word Boundary
CE
tCEZ
OE
tOER

tOEZ
RDY
Case 4 : Start from "16N+15" address group CR setting : A14=1, A13=0, A12=1, A11=0
14th rising edge CLK

A0-A23 Data Bus : CLK
Aa

3F
10
11
00
3F
10
11
12
AVD
Additional 13 Cycle for First Word Boundary
CE
OE
tOER

RDY
NOTE : 1) Address boundary occurs every 16 words beginning at address 000000FH , 000001FH , 000002FH , etc. 2) Address 000000H is also a boundary crossing. 3) No additional clock cycles are needed except for 1st boundary crossing.
Figure 22: Crossing of first word boundary in burst read mode.
- 46 -
K8A56(57)15ET(B)(Z)C
[Table 16] Top Boot Block Address Table Bank Block BA258 BA257 BA256 BA255 BA254 BA253 BA252 BA251 BA250 Bank 0 BA249 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 Bank 1 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 BA221 BA220 Bank 2 BA219 BA218 BA217 BA216 BA215 BA214
datasheet NOR FLASH MEMORY
Block Size 16 kwords 16 kwords 16 kwords 16 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range FFC000h-FFFFFFh FF8000h-FFBFFFh FF4000h-FF7FFFh FF0000h-FF3FFFh FE0000h-FEFFFFh FD0000h-FDFFFFh FC0000h-FCFFFFh FB0000h-FBFFFFh FA0000h-FAFFFFh F90000h-F9FFFFh F80000h-F8FFFFh F70000h-F7FFFFh F60000h-F6FFFFh F50000h-F5FFFFh F40000h-F4FFFFh F30000h-F3FFFFh F20000h-F2FFFFh F10000h-F1FFFFh F00000h-F0FFFFh EF0000h-EFFFFFh EE0000h-EEFFFFh ED0000h-EDFFFFh EC0000h-ECFFFFh EB0000h-EBFFFFh EA0000h-EAFFFFh E90000h-E9FFFFh E80000h-E8FFFFh E70000h-E7FFFFh E60000h-E6FFFFh E50000h-E5FFFFh E40000h-E4FFFFh E30000h-E3FFFFh E20000h-E2FFFFh E10000h-E1FFFFh E00000h-E0FFFFh DF0000h-DFFFFFh DE0000h-DEFFFFh DD0000h-DDFFFFh DC0000h-DCFFFFh DB0000h-DBFFFFh DA0000h-DAFFFFh D90000h-D9FFFFh D80000h-D8FFFFh D70000h-D7FFFFh D60000h-D6FFFFh
Rev. 1.0
- 47 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range D50000h-D5FFFFh D40000h-D4FFFFh D30000h-D3FFFFh D20000h-D2FFFFh D10000h-D1FFFFh D00000h-D0FFFFh CF0000h-CFFFFFh CE0000h-CEFFFFh CD0000h-CDFFFFh CC0000h-CCFFFFh CB0000h-CBFFFFh CA0000h-CAFFFFh C90000h-C9FFFFh C80000h-C8FFFFh C70000h-C7FFFFh C60000h-C6FFFFh C50000h-C5FFFFh C40000h-C4FFFFh C30000h-C3FFFFh C20000h-C2FFFFh C10000h-C1FFFFh C00000h-C0FFFFh BF0000h-BFFFFFh BE0000h-BEFFFFh BD0000h-BDFFFFh BC0000h-BCFFFFh BB0000h-BBFFFFh BA0000h-BAFFFFh B90000h-B9FFFFh B80000h-B8FFFFh B70000h-B7FFFFh B60000h-B6FFFFh B50000h-B5FFFFh B40000h-B4FFFFh B30000h-B3FFFFh B20000h-B2FFFFh B10000h-B1FFFFh B00000h-B0FFFFh AF0000h-AFFFFFh AE0000h-AEFFFFh AD0000h-ADFFFFh AC0000h-ACFFFFh AB0000h-ABFFFFh AA0000h-AAFFFFh A90000h-A9FFFFh
Rev. 1.0
Bank
Block BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 BA181 BA180 BA179 BA178 BA177 BA176 BA175 BA174 BA173
Bank 2
Bank 3
Bank 4
Bank 5
BA172 BA171 BA170 BA169
- 48 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range A80000h-A8FFFFh A70000h-A7FFFFh A60000h-A6FFFFh A50000h-A5FFFFh A40000h-A4FFFFh A30000h-A3FFFFh A20000h-A2FFFFh A10000h-A1FFFFh A00000h-A0FFFFh 9F0000h-9FFFFFh 9E0000h-9EFFFFh 9D0000h-9DFFFFh 9C0000h-9CFFFFh 9B0000h-9BFFFFh 9A0000h-9AFFFFh 990000h-99FFFFh 980000h-98FFFFh 970000h-97FFFFh 960000h-96FFFFh 950000h-95FFFFh 940000h-94FFFFh 930000h-93FFFFh 920000h-92FFFFh 910000h-91FFFFh 900000h-90FFFFh 8F0000h-8FFFFFh 8E0000h-08EFFFFh 8D0000h-8DFFFFh 8C0000h-8CFFFFh 8B0000h-8BFFFFh 8A0000h-8AFFFFh 890000h-89FFFFh 880000h-88FFFFh 870000h-87FFFFh 860000h-86FFFFh 850000h-85FFFFh 840000h-84FFFFh 830000h-83FFFFh 820000h-82FFFFh 810000h-81FFFFh 800000h-80FFFFh 7F0000h-7FFFFFh 7E0000h-7EFFFFh 7D0000h-7DFFFFh 7C0000h-7CFFFFh
Rev. 1.0
Bank
Block BA168 BA167 BA166 BA165
Bank 5
BA164 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 BA125 BA124
Bank 6
Bank 7
Bank 8
- 49 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 7B0000h-7BFFFFh 7A0000h-7AFFFFh 790000h-79FFFFh 780000h-78FFFFh 770000h-77FFFFh 760000h-76FFFFh 750000h-75FFFFh 740000h-74FFFFh 730000h-73FFFFh 720000h-72FFFFh 710000h-71FFFFh 700000h-70FFFFh 6F0000h-6FFFFFh 6E0000h-6EFFFFh 6D0000h-6DFFFFh 6C0000h-6CFFFFh 6B0000h-6BFFFFh 6A0000h-6AFFFFh 690000h-69FFFFh 680000h-68FFFFh 670000h-67FFFFh 660000h-66FFFFh 650000h-65FFFFh 640000h-64FFFFh 630000h-63FFFFh 620000h-62FFFFh 610000h-61FFFFh 600000h-60FFFFh 5F0000h-5FFFFFh 5E0000h-5EFFFFh 5D0000h-5DFFFFh 5C0000h-5CFFFFh 5B0000h-5BFFFFh 5A0000h-5AFFFFh 590000h-59FFFFh 580000h-58FFFFh 570000h-57FFFFh 560000h-56FFFFh 550000h-55FFFFh 540000h-54FFFFh 530000h-53FFFFh 520000h-52FFFFh 510000h-51FFFFh 500000h-50FFFFh
Rev. 1.0
Bank
Block BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 BA80
Bank 8
Bank 9
Bank10
- 50 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 4F0000h-4FFFFFh 4E0000h-4EFFFFh 4D0000h-4DFFFFh 4C0000h-4CFFFFh 4B0000h-4BFFFFh 4A0000h-4AFFFFh 490000h-49FFFFh 480000h-48FFFFh 470000h-47FFFFh 460000h-46FFFFh 450000h-45FFFFh 440000h-44FFFFh 430000h-43FFFFh 420000h-42FFFFh 410000h-41FFFFh 400000h-40FFFFh 3F0000h-3FFFFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-38FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh
Rev. 1.0
Bank
Block BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42
Bank 11
Bank 12
Bank 13
BA41 BA40 BA39 BA38 BA37 BA36 BA35
- 51 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh
Rev. 1.0
Bank Bank 13
Block BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
Bank 14
Bank 15
[Table 17] OTP Block Addresses Block Address A23 ~ A8 FFFFh
OTP
Block Size 512words
(x16) Address Range* FFFE00h-FFFFFFh
After entering OTP Block, any issued addresses should be in the range of OTP block address.
- 52 -
K8A56(57)15ET(B)(Z)C
[Table 18] Bottom Boot Block Address Table Bank Block BA258 BA257 BA256 BA255 BA254 BA253 BA252 Bank 15 BA251 BA250 BA249 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 BA240 BA239 BA238 BA237 BA236 Bank 14 BA235 BA234 BA233 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 BA221 Bank 13 BA220 BA219 BA218 BA217 BA216 BA215 BA214
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range FF0000h-FFFFFFh FE0000h-FEFFFFh FD0000h-FDFFFFh FC0000h-FCFFFFh FB0000h-FBFFFFh FA0000h-FAFFFFh F90000h-F9FFFFh F80000h-F8FFFFh F70000h-F7FFFFh F60000h-F6FFFFh F50000h-F5FFFFh F40000h-F4FFFFh F30000h-F3FFFFh F20000h-F2FFFFh F10000h-F1FFFFh F00000h-F0FFFFh EF0000h-EFFFFFh EE0000h-EEFFFFh ED0000h-EDFFFFh EC0000h-ECFFFFh EB0000h-EBFFFFh EA0000h-EAFFFFh E90000h-E9FFFFh E80000h-E8FFFFh E70000h-E7FFFFh E60000h-E6FFFFh E50000h-E5FFFFh E40000h-E4FFFFh E30000h-E3FFFFh E20000h-E2FFFFh E10000h-E1FFFFh E00000h-E0FFFFh DF0000h-DFFFFFh DE0000h-DEFFFFh DD0000h-DDFFFFh DC0000h-DCFFFFh DB0000h-DBFFFFh DA0000h-DAFFFFh D90000h-D9FFFFh D80000h-D8FFFFh D70000h-D7FFFFh D60000h-D6FFFFh D50000h-D5FFFFh D40000h-D4FFFFh D30000h-D3FFFFh
Rev. 1.0
- 53 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range D20000h-D2FFFFh D10000h-D1FFFFh D00000h-D0FFFFh CF0000h-CFFFFFh CE0000h-CEFFFFh CD0000h-CDFFFFh CC0000h-CCFFFFh CB0000h-CBFFFFh CA0000h-CAFFFFh C90000h-C9FFFFh C80000h-C8FFFFh C70000h-C7FFFFh C60000h-C6FFFFh C50000h-C5FFFFh C40000h-C4FFFFh C30000h-C3FFFFh C20000h-C2FFFFh C10000h-C1FFFFh C00000h-C0FFFFh BF0000h-BFFFFFh BE0000h-BEFFFFh BD0000h-BDFFFFh BC0000h-BCFFFFh BB0000h-BBFFFFh BA0000h-BAFFFFh B90000h-B9FFFFh B80000h-B8FFFFh B70000h-B7FFFFh B60000h-B6FFFFh B50000h-B5FFFFh B40000h-B4FFFFh B30000h-B3FFFFh B20000h-B2FFFFh B10000h-B1FFFFh B00000h-B0FFFFh AF0000h-AFFFFFh AE0000h-AEFFFFh AD0000h-ADFFFFh AC0000h-ACFFFFh AB0000h-ABFFFFh AA0000h-AAFFFFh A90000h-A9FFFFh A80000h-A8FFFFh A70000h-A7FFFFh A60000h-A6FFFFh
Rev. 1.0
Bank Bank 13
Block BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 BA181 BA180 BA179 BA178 BA177 BA176 BA175 BA174 BA173 BA172 BA171 BA170 BA169
Bank 12
Bank 11
Bank 10
- 54 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range A50000h-A5FFFFh A40000h-A4FFFFh A30000h-A3FFFFh A20000h-A2FFFFh A10000h-A1FFFFh A00000h-A0FFFFh 9F0000h-9FFFFFh 9E0000h-9EFFFFh 9D0000h-9DFFFFh 9C0000h-9CFFFFh 9B0000h-9BFFFFh 9A0000h-9AFFFFh 990000h-99FFFFh 980000h-98FFFFh 970000h-97FFFFh 960000h-96FFFFh 950000h-95FFFFh 940000h-94FFFFh 930000h-93FFFFh 920000h-92FFFFh 910000h-91FFFFh 900000h-90FFFFh 8F0000h-8FFFFFh 8E0000h-08EFFFFh 8D0000h-8DFFFFh 8C0000h-8CFFFFh 8B0000h-8BFFFFh 8A0000h-8AFFFFh 890000h-89FFFFh 880000h-88FFFFh 870000h-87FFFFh 860000h-86FFFFh 850000h-85FFFFh 840000h-84FFFFh 830000h-83FFFFh 820000h-82FFFFh 810000h-81FFFFh 800000h-80FFFFh 7F0000h-7FFFFFh 7E0000h-7EFFFFh 7D0000h-7DFFFFh 7C0000h-7CFFFFh 7B0000h-7BFFFFh 7A0000h-7AFFFFh 790000h-79FFFFh
Rev. 1.0
Bank
Block BA168 BA167 BA166 BA165 BA164 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128
Bank 10
Bank 9
Bank 8
Bank 7
BA127 BA126 BA125 BA124
- 55 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 780000h-78FFFFh 770000h-77FFFFh 760000h-76FFFFh 750000h-75FFFFh 740000h-74FFFFh 730000h-73FFFFh 720000h-72FFFFh 710000h-71FFFFh 700000h-70FFFFh 6F0000h-6FFFFFh 6E0000h-6EFFFFh 6D0000h-6DFFFFh 6C0000h-6CFFFFh 6B0000h-6BFFFFh 6A0000h-6AFFFFh 690000h-69FFFFh 680000h-68FFFFh 670000h-67FFFFh 660000h-66FFFFh 650000h-65FFFFh 640000h-64FFFFh 630000h-63FFFFh 620000h-62FFFFh 610000h-61FFFFh 600000h-60FFFFh 5F0000h-5FFFFFh 5E0000h-5EFFFFh 5D0000h-5DFFFFh 5C0000h-5CFFFFh 5B0000h-5BFFFFh 5A0000h-5AFFFFh 590000h-59FFFFh 580000h-58FFFFh 570000h-57FFFFh 560000h-56FFFFh 550000h-55FFFFh 540000h-54FFFFh 530000h-53FFFFh 520000h-52FFFFh 510000h-51FFFFh 500000h-50FFFFh 4F0000h-4FFFFFh 4E0000h-4EFFFFh 4D0000h-4DFFFFh
Rev. 1.0
Bank
Block BA123 BA122 BA121 BA120
Bank 7
BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 BA85 BA84 BA83 BA82
Bank 6
Bank5
Bank4
BA81 BA80
- 56 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 4C0000h-4CFFFFh 4B0000h-4BFFFFh 4A0000h-4AFFFFh 490000h-49FFFFh 480000h-48FFFFh 470000h-47FFFFh 460000h-46FFFFh 450000h-45FFFFh 440000h-44FFFFh 430000h-43FFFFh 420000h-42FFFFh 410000h-41FFFFh 400000h-40FFFFh 3F0000h-3FFFFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-38FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh
Rev. 1.0
Bank
Block BA79 BA78 BA77 BA76 BA75 BA74
Bank 4
BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35
Bank 3
Bank 2
- 57 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 16 kwords 16 kwords 16 kwords 16 kwords (x16) Address Range 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 00C000h-00FFFFh 008000h-00BFFFh 004000h-007FFFh 000000h-003FFFh
Rev. 1.0
Bank
Block BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10
Bank 1
Bank 0
BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
[Table 19] Bottom Boot OTP Block Addresses Block Address A23 ~ A8 0000h
OTP
Block Size 512 words
(x16) Address Range* 000000h-0001FFh
After entering OTP Block, any issued addresses should be in the range of OTP block address.
- 58 -
K8A56(57)15ET(B)(Z)C
[Table 20] Uniform Block Address Table Bank Block BA255 BA254 BA253 BA252 BA251 BA250 BA249 Bank 0 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 Bank 1 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 BA221 BA220 Bank 2 BA219 BA218 BA217 BA216 BA215 BA214
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 0FF0000h-0FFFFFFh 0FE0000h-0FEFFFFh 0FD0000h-0FDFFFFh 0FC0000h-0FCFFFFh 0FB0000h-0FBFFFFh 0FA0000h-0FAFFFFh 0F90000h-0F9FFFFh 0F80000h-0F8FFFFh 0F70000h-0F7FFFFh 0F60000h-0F6FFFFh 0F50000h-0F5FFFFh 0F40000h-0F4FFFFh 0F30000h-0F3FFFFh 0F20000h-0F2FFFFh 0F10000h-0F1FFFFh 0F00000h-0F0FFFFh 0EF0000h-0EFFFFFh 0EE0000h-0EEFFFFh 0ED0000h-0EDFFFFh 0EC0000h-0ECFFFFh 0EB0000h-0EBFFFFh 0EA0000h-0EAFFFFh 0E90000h-0E9FFFFh 0E80000h-0E8FFFFh 0E70000h-0E7FFFFh 0E60000h-0E6FFFFh 0E50000h-0E5FFFFh 0E40000h-0E4FFFFh 0E30000h-0E3FFFFh 0E20000h-0E2FFFFh 0E10000h-0E1FFFFh 0E00000h-0E0FFFFh 0DF0000h-0DFFFFFh 0DE0000h-0DEFFFFh 0DD0000h-0DDFFFFh 0DC0000h-0DCFFFFh 0DB0000h-0DBFFFFh 0DA0000h-0DAFFFFh 0D90000h-0D9FFFFh 0D80000h-0D8FFFFh 0D70000h-0D7FFFFh 0D60000h-0D6FFFFh
Rev. 1.0
- 59 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 0D50000h-0D5FFFFh 0D40000h-0D4FFFFh 0D30000h-0D3FFFFh 0D20000h-0D2FFFFh 0D10000h-0D1FFFFh 0D00000h-0D0FFFFh 0CF0000h-0CFFFFFh 0CE0000h-0CEFFFFh 0CD0000h-0CDFFFFh 0CC0000h-0CCFFFFh 0CB0000h-0CBFFFFh 0CA0000h-0CAFFFFh 0C90000h-0C9FFFFh 0C80000h-0C8FFFFh 0C70000h-0C7FFFFh 0C60000h-0C6FFFFh 0C50000h-0C5FFFFh 0C40000h-0C4FFFFh 0C30000h-0C3FFFFh 0C20000h-0C2FFFFh 0C10000h-0C1FFFFh 0C00000h-0C0FFFFh 0BF0000h-0BFFFFFh 0BE0000h-0BEFFFFh 0BD0000h-0BDFFFFh 0BC0000h-0BCFFFFh 0BB0000h-0BBFFFFh 0BA0000h-0BAFFFFh 0B90000h-0B9FFFFh 0B80000h-0B8FFFFh 0B70000h-0B7FFFFh 0B60000h-0B6FFFFh 0B50000h-0B5FFFFh 0B40000h-0B4FFFFh 0B30000h-0B3FFFFh 0B20000h-0B2FFFFh 0B10000h-0B1FFFFh 0B00000h-0B0FFFFh 0AF0000h-0AFFFFFh 0AE0000h-0AEFFFFh 0AD0000h-0ADFFFFh 0AC0000h-0ACFFFFh 0AB0000h-0ABFFFFh 0AA0000h-0AAFFFFh 0A90000h-0A9FFFFh
Rev. 1.0
Bank
Block BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 BA181 BA180 BA179 BA178 BA177 BA176 BA175 BA174 BA173
Bank 2
Bank 3
Bank 4
Bank 5
BA172 BA171 BA170 BA169
- 60 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 0A80000h-0A8FFFFh 0A70000h-0A7FFFFh 0A60000h-0A6FFFFh 0A50000h-0A5FFFFh 0A40000h-0A4FFFFh 0A30000h-0A3FFFFh 0A20000h-0A2FFFFh 0A10000h-0A1FFFFh 0A00000h-0A0FFFFh 09F0000h-09FFFFFh 09E0000h-09EFFFFh 09D0000h-09DFFFFh 09C0000h-09CFFFFh 09B0000h-09BFFFFh 09A0000h-09AFFFFh 0990000h-099FFFFh 0980000h-098FFFFh 0970000h-097FFFFh 0960000h-096FFFFh 0950000h-095FFFFh 0940000h-094FFFFh 0930000h-093FFFFh 0920000h-092FFFFh 0910000h-091FFFFh 0900000h-090FFFFh 08F0000h-08FFFFFh 08E0000h-08EFFFFh 08D0000h-08DFFFFh 08C0000h-08CFFFFh 08B0000h-08BFFFFh 08A0000h-08AFFFFh 0890000h-089FFFFh 0880000h-088FFFFh 0870000h-087FFFFh 0860000h-086FFFFh 0850000h-085FFFFh 0840000h-084FFFFh 0830000h-083FFFFh 0820000h-082FFFFh 0810000h-081FFFFh 0800000h-080FFFFh 07F0000h-07FFFFFh 07E0000h-07EFFFFh 07D0000h-07DFFFFh 07C0000h-07CFFFFh
Rev. 1.0
Bank
Block BA168 BA167 BA166 BA165
Bank 5
BA164 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 BA125 BA124
Bank 6
Bank 7
Bank 8
- 61 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 07B0000h-07BFFFFh 07A0000h-07AFFFFh 0790000h-079FFFFh 0780000h-078FFFFh 0770000h-077FFFFh 0760000h-076FFFFh 0750000h-075FFFFh 0740000h-074FFFFh 0730000h-073FFFFh 0720000h-072FFFFh 0710000h-071FFFFh 0700000h-070FFFFh 06F0000h-06FFFFFh 06E0000h-06EFFFFh 06D0000h-06DFFFFh 06C0000h-06CFFFFh 06B0000h-06BFFFFh 06A0000h-06AFFFFh 0690000h-069FFFFh 0680000h-068FFFFh 0670000h-067FFFFh 0660000h-066FFFFh 0650000h-065FFFFh 0640000h-064FFFFh 0630000h-063FFFFh 0620000h-062FFFFh 0610000h-061FFFFh 0600000h-060FFFFh 05F0000h-05FFFFFh 05E0000h-05EFFFFh 05D0000h-05DFFFFh 05C0000h-05CFFFFh 05B0000h-05BFFFFh 05A0000h-05AFFFFh 0590000h-059FFFFh 0580000h-058FFFFh 0570000h-057FFFFh 0560000h-056FFFFh 0550000h-055FFFFh 0540000h-054FFFFh 0530000h-053FFFFh 0520000h-052FFFFh 0510000h-051FFFFh 0500000h-050FFFFh
Rev. 1.0
Bank
Block BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 BA80
Bank 8
Bank 9
Bank10
- 62 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 04F0000h-04FFFFFh 04E0000h-04EFFFFh 04D0000h-04DFFFFh 04C0000h-04CFFFFh 04B0000h-04BFFFFh 04A0000h-04AFFFFh 0490000h-049FFFFh 0480000h-048FFFFh 0470000h-047FFFFh 0460000h-046FFFFh 0450000h-045FFFFh 0440000h-044FFFFh 0430000h-043FFFFh 0420000h-042FFFFh 0410000h-041FFFFh 0400000h-040FFFFh 03F0000h-03FFFFFh 03E0000h-03EFFFFh 03D0000h-03DFFFFh 03C0000h-03CFFFFh 03B0000h-03BFFFFh 03A0000h-03AFFFFh 0390000h-039FFFFh 0380000h-038FFFFh 0370000h-037FFFFh 0360000h-036FFFFh 0350000h-035FFFFh 0340000h-034FFFFh 0330000h-033FFFFh 0320000h-032FFFFh 0310000h-031FFFFh 0300000h-030FFFFh 02F0000h-02FFFFFh 02E0000h-02EFFFFh 02D0000h-02DFFFFh 02C0000h-02CFFFFh 02B0000h-02BFFFFh 02A0000h-02AFFFFh 0290000h-029FFFFh 0280000h-028FFFFh 0270000h-027FFFFh 0260000h-026FFFFh 0250000h-025FFFFh 0240000h-024FFFFh 0230000h-023FFFFh
Rev. 1.0
Bank
Block BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42
Bank 11
Bank 12
Bank 13
BA41 BA40 BA39 BA38 BA37 BA36 BA35
- 63 -
K8A56(57)15ET(B)(Z)C
datasheet NOR FLASH MEMORY
Block Size 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords 64 kwords (x16) Address Range 0220000h-022FFFFh 0210000h-021FFFFh 0200000h-020FFFFh 01F0000h-01FFFFFh 01E0000h-01EFFFFh 01D0000h-01DFFFFh 01C0000h-01CFFFFh 01B0000h-01BFFFFh 01A0000h-01AFFFFh 0190000h-019FFFFh 0180000h-018FFFFh 0170000h-017FFFFh 0160000h-016FFFFh 0150000h-015FFFFh 0140000h-014FFFFh 0130000h-013FFFFh 0120000h-012FFFFh 0110000h-011FFFFh 0100000h-010FFFFh 00F0000h-00FFFFFh 00E0000h-00EFFFFh 00D0000h-00DFFFFh 00C0000h-00CFFFFh 00B0000h-00BFFFFh 00A0000h-00AFFFFh 0090000h-009FFFFh 0080000h-008FFFFh 0070000h-007FFFFh 0060000h-006FFFFh 0050000h-005FFFFh 0040000h-004FFFFh 0030000h-003FFFFh 0020000h-002FFFFh 0010000h-001FFFFh 0000000h-000FFFFh
Rev. 1.0
Bank Bank 13
Block BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
Bank 14
Bank 15
[Table 21] Uniform OTP Block Addresses Block Address A23 ~ A8 FFFFh
OTP
Block Size 512 words
(x16) Address Range* FFFE00h-FFFFFFh
After entering OTP Block, any issued addresses should be in the range of OTP block address.
- 64 -

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